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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20880-4E
FLASH MEMORY
CMOS
16M (2M x 8/1M x 16) BIT
MBM29DL16XTE/BE70/90
s FEATURES
Dual Operation
* 0.23 m Process Technology * Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to "MBM29DL16XTE/BE Device Bank Divisions Table" in sGENERAL DESCRIPTION) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program (Continued)
s PRODUCT LINE UP
Part No. Address Access Time (Max) CE Access Time (Max) OE Access Time (Max) Power Supply Voltage MBM29DL16XTE/BE70 70 ns 70 ns 30 ns 3.0 V
+0.6 V -0.3 V
MBM29DL16XTE/BE90 90 ns 90 ns 35 ns
s PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
48-pin plastic FBGA
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-48P-M11)
MBM29DL16XTE/BE70/90
(Continued) * Single 3.0 V read, program, and erase Minimizes system level power requirements * Compatible with JEDEC-standard commands Uses same software commands as E2PROMs * Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(1) (Package suffix: TN - Normal Bend Type, TR - Reversed Bend Type) 48-pin FBGA (Package suffix: PBT) * Minimum 100,000 program/erase cycles * High performance 70 ns maximum access time * Sector erase architecture Eight 4K word and thirty one 32K word sectors in word mode Eight 8K byte and thirty one 64K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture T = Top sector B = Bottom sector * HiddenROM region 64K byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC input pin At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status At VACC, increases program performance * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC write inhibit 2.5 V * Program Suspend/Resume Suspends the program operation to allow a read in another sector with in the same device * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Sector group protection Hardware method disables any combination of sector groups from program or erase operations * Sector Group Protection Set function by Extended sector group protection command * Fast Programming Function by Extended Command * Temporary sector group unprotection Temporary sector group unprotection via the RESET pin. * In accordance with CFI (Common Flash Memory Interface)
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MBM29DL16XTE/BE70/90
s GENERAL DESCRIPTION
The MBM29DL16XTE/BE are a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29DL16XTE/BE are offered in a 48-pin TSOP(1) and 48-pin FBGA Package. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. MBM29DL16XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate memory arrays for operations. It is the Fujitsu's standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. In the MBM29DL16XTE/BE, a new design concept is implemented, so called "Sliding Bank Architecture". Under this concept, the MBM29DL16XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size combinations; 0.5 Mb/15.5 Mb, 2 Mb/14 Mb, 4 Mb/12 Mb, 8 Mb/8 Mb. The standard MBM29DL16XTE/BE offer access times 70 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29DL16XTE/BE are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29DL16XTE/BE are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29DL16XTE/BE are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29DL16XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
3
MBM29DL16XTE/BE70/90
MBM29DL16XTE/BE Device Bank Divisions Table Device Part Number MBM29DL161TE/BE MBM29DL162TE/BE x 8/x 16 MBM29DL163TE/BE MBM29DL164TE/BE 4 Mbit 8 Mbit Organization Bank 1 Megabits 0.5 Mbit 2 Mbit Sector Sizes Eight 8K byte/4K word Eight 8K byte/4K word, three 64K byte/32K word Eight 8K byte/4K word, seven 64K byte/32K word Eight 8K byte/4K word, fifteen 64K byte/32K word Megabits 15.5 Mbit 14 Mbit 12 Mbit 8 Mbit Bank 2 Sector Sizes Thirty-one 64K byte/32K word Twenty-eight 64K byte/32K word Twenty-four 64K byte/32K word Sixteen 64K byte/32K word
4
MBM29DL16XTE/BE70/90
s PIN ASSIGNMENTS
TSOP(1)
A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0
Normal Bend
(FPT-48P-M19)
A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP/ACC N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16
(Marking Side)
Reverse Bend
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
(FPT-48P-M20)
(Continued)
5
MBM29DL16XTE/BE70/90
(Continued)
FBGA
(TOP VIEW)
Marking side
A6 A13 A5 A9 A4 WE A3 A2 A7 A1 A3 B6 A12 B5 A8 C6 A14 C5 A10 D6 A15 D5 A11 D4 A19 D3 D2 A5 D1 A1 E6 A16 E5 DQ7 E4 DQ5 E3 E2 DQ0 E1 A0 F6 G6 H6 BYTE DQ15/A-1 VSS F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS
C4 B4 RESET N.C. B3 B2 A17 B1 A4 C3 C2 A6 C1 A2
RY/BY WP/ACC A18
N.C. DQ2
(BGA-48P-M11)
s PIN DESCRIPTIONS
Pin Name A19 to A0, A-1 DQ15 to DQ0 CE OE WE RESET Address Input Data Input/Output Chip Enable Output Enable Write Enable Hardware Reset Pin/ Temporary Sector Group Unprotection Function Pin Name RY/BY BYTE WP/ACC VSS VCC N.C. Function Ready/Busy Output Selects 8-bit or 16-bit mode Hardware Write Protection/ Program Acceleration Device Ground Device Power Supply No Internal Connection
6
MBM29DL16XTE/BE70/90
s BLOCK DIAGRAM
VCC VSS
Bank 2 Address A19 to A0 (A-1)
Cell Matrix (Bank 2)
X-Decoder RY/BY State Control & Command Register Status Control DQ15 to DQ0
RESET WE CE OE BYTE WP/ACC DQ15 to DQ0
X-Decoder Y-Gating & Data Latch
Bank 1 Address
Cell Matrix (Bank 1)
s LOGIC SYMBOL
A-1 20 A19 to A0 DQ15 to DQ0 CE OE WE RESET BYTE WP/ACC RY/BY 16 or 8
Y-Gating & Data Latch
7
MBM29DL16XTE/BE70/90
s DEVICE BUS OPERATION
MBM29DL16XTE/BE User Bus Operations Table (BYTE = VIH) Operation Auto-Select Manufacturer Code*1 Auto-Select Device Code*1 Read*3 Standby Output Disable Write (Program/Erase) Enable Sector Group Protection*2, *4 Verify Sector Group Protection*2, *4 Temporary Sector Group Unprotection* Reset (Hardware) / Standby Boot Block Sector Write Protection Legend: L = VIL, H = VIH, X = VIL or VIH,
5
CE OE WE L L L H L L L L X X X L L L X H H VID L X X X H X X X H H H X H L
A0 L H A0 X X A0 L L X X X
A1 L L A1 X X A1 H H X X X
A6 L L A6 X X A6 L L X X X
A9 VID VID A9 X X A9 VID VID X X X
DQ15 to DQ0 RESET WP/ACC Code Code DOUT High-Z High-Z DIN X Code X High-Z X H H H H H H H H VID L X X X X X X X X X X X L
= Pulse input. See sDC CHARACTERISTICS for voltage levels.
*1: Manufacturer and device codes are accessed via a command register write sequence. See "MBM29DL16XTE/ BE Command Definitions Table". *2: Refer to "Sector Group Protection" in sFUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = +2.7 V to +3.6 V *5: Also used for the extended sector group protection. MBM29DL16XTE/BE User Bus Operations Table (BYTE = VIL) Operation Auto-Select Manufacturer Code*1 Auto-Select Device Code*1 Read*
3
CE
OE WE DQ15/ A-1
A0
A1
A6
A9
DQ7 to DQ0 RESET WP/ACC
L L L H L L L L
5
L L L X H H VID L X X X
H H H X H L
L L A-1 X X A-1 L
L H A0 X X A0 L L X X X
L L A1 X X A1 H H X X X
L L A6 X X A6 L L X X X
VID VID A9 X X A9 VID VID X X X
Code Code DOUT High-Z High-Z DIN X Code X High-Z X
H H H H H H H H VID L X
X X X X X X X X X X L
Standby Output Disable Write (Program/Erase) Enable Sector Group Protection*2, *4 Verify Sector Group Protection* * Reset (Hardware) / Standby Boot Block Sector Write Protection Legend: L = VIL, H = VIH, X = VIL or VIH,
2, 4
H X X X
L X X X
Temporary Sector Group Unprotection*
X X X
= Pulse input. See sDC CHARACTERISTICS for voltage levels.
*1: Manufacturer and device codes are accessed via a command register write sequence. See "MBM29DL16XTE/ BE Command Definitions Table". *2: Refer to "Sector Group Protection" in sFUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = +2.7 V to +3.6 V *5: Also used for the extended sector group protection. 8
MBM29DL16XTE/BE70/90
MBM29DL16XTE/BE Command Definitions Table Command Sequence
Read/Reset*1 Read/Reset*1 Bus Write Cycles Req'd
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXh F0h -- 2AAh 555h 2AAh AAh AAAh 555h AAh B0h 30h AAh AAh B0h 30h AAh A0h 90h 60h 2AAh 555h -- -- 2AAh 555h 2AAh 555h -- -- 2AAh 555h PA XXXh SPA 55h -- -- 55h 55h -- -- 55h PD *6 F0h 60h 555h AAAh BA BA 555h AAAh 555h AAAh BA BA 555h AAAh XXXh BA XXXh 55h -- 55h -- 555h AAAh (BA) 555h (BA) AAAh 555h AAAh -- -- 555h AAAh 555h AAAh -- -- 555h AAAh -- -- SPA -- F0h -- RA*7 -- RD*7 -- -- -- -- -- -- -- --
Word Byte Word Byte Word
1 3
555h AAh AAAh 555h
Autoselect
3
Byte Word Byte
90h
IA*7
ID*7
--
--
--
--
Program
4 1 1 6 6 1 1 3 2 2 3
A0h -- -- 80h 80h -- -- 20h -- --
PA
PD
-- -- -- 2AAh 555h 2AAh 555h -- -- -- -- -- --
-- -- -- 55h 55h -- -- -- -- -- --
-- -- -- 555h AAAh SA -- -- -- -- -- --
-- -- -- 10h 30h -- -- -- -- -- --
Program Suspend Program Resume Chip Erase
Word Byte Word Byte
Sector Erase
Erase Suspend Erase Resume
Set to Fast Mode Fast Program*2 Reset from Fast Mode*2 Extended Sector Group Protection*3
-- -- -- -- 555h AAh AAAh 555h AAh AAAh -- -- -- -- -- -- -- -- -- --
Word Byte Word Byte Word Byte Word Byte Word
40h SPA*7 SD*7
Query *
4
1
Byte Word Byte Word Byte Word Byte Word
HiddenROM Entry HiddenROM Program*5 HiddenROM Erase*5
3 4 6
(BA) 55h 98h (BA) AAh 555h AAh AAAh 555h AAh AAAh 555h AAh AAAh 555h AAh AAAh
-- 2AAh 555h 2AAh 555h 2AAh 555h 2AAh
--
-- 555h AAAh 555h AAAh 555h AAAh
(HRBA)
--
--
--
--
--
--
--
55h 55h 55h
88h A0h 80h
-- PA (HRA)
-- PD
-- -- 2AAh 555h --
-- -- 55h
-- -- HRA
-- -- 30h
555h AAh AAAh XXXh 00h
HiddenROM Exit*5
4
Byte
55h 555h
555h
(HRBA)
90h
--
--
--
AAAh
9
MBM29DL16XTE/BE70/90
Notes: * * * Address bits A19 to A11 = X = "H" or "L" for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA). Bus operations are defined in "MBM29DL16XTE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)". RA: Address of the memory location to be read IA : Autoselect read address that sets both the bank address specified at (A19, A18, A17, A16, A15) and all the other A6, A1, A0, (A-1). PA: Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA: Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA: Bank Address (A19 to A15) RD: Data read from location RA during read operation. ID : Device code/manufacture code for the address located by IA. PD: Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SPA: Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). SD: Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA: Address of the HiddenROM area 29DL16XTE (Top Boot Type) Word Mode: 0F8000h to 0FFFFFh Byte Mode: 1F0000h to 1FFFFFh 29DL16XBE (Bottom Boot Type) Word Mode: 000000h to 007FFFh Byte Mode: 000000h to 00FFFFh HRBA: Bank Address of the HiddenROM area 29DL16XTE (Top Boot Type) :A19 = A18= A17 = A16 = A15 = VIH 29DL16XBE (Bottom Boot Type) :A19 = A18= A17 = A16 = A15 = VIL The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A10 to A0 Byte Mode: AAAh or 555h to addresses A10 to A0 and A-1 Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Command combinations not described in Command Definitions table are illegal.
*
*
*
*
*
* *
*1: Both of these reset commands are equivalent. *2: This command is valid during Fast Mode. *3: This command is valid while RESET = VID (except during HiddenROM MODE). *4: The valid addresses are A6 to A0. *5: This command is valid during HiddenROM mode. *6: The data "00h" is also acceptable. *7: The fourth bus cycle is only for read.
10
MBM29DL16XTE/BE70/90
MBM29DL161TE/BE Sector Group Protection Verify Autoselect Codes Table Type Byte Manufacture's Code Word Byte MBM29DL161TE Device Code MBM29DL161BE Word Sector Group Protection Byte Sector Group Word Addresses VIL VIH VIL X 0001h*2 Word Byte BA*3 VIL VIL VIH X VIL 2239h 01h*2 BA*3 VIL VIL VIH X VIL 2236h 39h BA*3 VIL VIL VIL X VIL 0004h 36h A19 to A12 A6 A1 A0 A-1*1 VIL Code (HEX) 04h
*1: A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3: When VID is applied to A9, both Bank1 and Bank2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. Extended Autoselect Code Table Type (B)* Manufacturer's Code (W) 0004h (B)* MBM29DL161TE Device Code MBM29DL161BE (W) 2239h 0 (B)* Sector Group Protection (W) 0001h (B) : Byte mode (W) : Word mode HI-Z : High-Z *: At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address.
0
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
04h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 1 1 1 1 0 0
0 0 1 1 1 1 0 0
0 0 0 0 1 1 0 0
1 1 1 1 0 0 0 0
0 0 1 1 0 0 0 0
0 0 0 0 1 1 1 1
36h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 0 0 1 0 0
(W) 2236h 0 (B)*
39h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 0 0 1 0 0
01h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 0 0 0 0 0 0
11
MBM29DL16XTE/BE70/90
MBM29DL162TE/BE Sector Group Protection Verify Autoselect Codes Table Type Byte Manufacture's Code Word Byte MBM29DL162TE Device Code MBM29DL162BE Word Sector Group Protection Byte Sector Group Word Addresses VIL VIH VIL X 0001h*2 Word Byte BA*3 VIL VIL VIH X VIL 222Eh 01h*2 BA*3 VIL VIL VIH X VIL 222Dh 2Eh BA*3 VIL VIL VIL X VIL 0004h 2Dh A19 to A12 A6 A1 A0 A-1*1 VIL Code (HEX) 04h
*1 : A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. Extended Autoselect Code Table Type (B)* Manufacturer's Code (W) 0004h 0 (B)* MBM29DL162TE Device Code MBM29DL162BE (W) 222Eh 0 (B)* Sector Group Protection (W) 0001h 0 (B) : Byte mode (W) : Word mode HI-Z : High-Z * : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 01h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 (W) 222Dh 0 (B)* 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 1 1 1 0 1 1 0 2Eh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 2Dh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 Code
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
04h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
0
0
0
1
0
0
12
MBM29DL16XTE/BE70/90
MBM29DL163TE/BE Sector Group Protection Verify Autoselect Codes Table Type Byte Manufacture's Code Word Byte MBM29DL163TE Device Code MBM29DL163BE Word Sector Group Protection Byte Sector Group Word Addresses VIL VIH VIL X 0001h*2 Word Byte BA*3 VIL VIL VIH X VIL 222Bh 01h*2 BA*3 VIL VIL VIH X VIL 2228h 2Bh BA*3 VIL VIL VIL X VIL 0004h 28h A19 to A12 A6 A1 A0 A-1*1 VIL Code (HEX) 04h
*1 : A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. Extended Autoselect Code Table Type (B)* Manufacturer's Code (W) 0004h 0 (B)* MBM29DL163TE Device Code MBM29DL163BE (W) 222Bh 0 (B)* 01h Sector Group Protection (W) 0001h 0 (B) : Byte mode (W) : Word mode HI-Z : High-Z * : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0
0
Code
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
04h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 1 1 1 1
0
0 0 0 0 0 0
0
0 0 1 1 1 1
0
1 1 0 0 0 0
0
0 0 0 0 1 1
0
0 0 0 0 1 1 1
28h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 1 0 0 0 1 0 0
(W) 2228h 0 (B)*
2Bh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
13
MBM29DL16XTE/BE70/90
MBM29DL164TE/BE Sector Group Protection Verify Autoselect Codes Table Type Byte Manufacture's Code Word Byte MBM29DL164TE Device Code MBM29DL164BE Word Sector Group Protection Byte Sector Group Word Addresses VIL VIH VIL X 0001h*2 Word Byte BA*3 VIL VIL VIH X VIL 2235h 01h*2 BA*3 VIL VIL VIH X VIL 2233h 35h BA*3 VIL VIL VIL X VIL 0004h 33h A19 to A12 A6 A1 A0 A-1*1 VIL Code (HEX) 04h
*1 : A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. Expanded Autoselect Code Table Type (B)* Manufacturer's Code (W) 0004h 0 (B)* MBM29DL164TE Device Code MBM29DL164BE (W) 2235h 0 (B)* Sector Group Protection (W) 0001h 0 (B) : Byte mode (W) : Word mode HI-Z : High-Z * : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 1 01h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 (W) 2233h 0 (B)* 0 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 35h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 33h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 Code
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
04h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
0
0
0
0
1
0
0
14
MBM29DL16XTE/BE70/90
s FLEXIBLE SECTOR-ERASE ARCHITECTURE
Sector Address Table (MBM29DL161TE) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address Sector Size (x8) (x16) Bank Address (Kbytes/ Address Range Address Range A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 0 0 0 0 0XXX 64/32 000000h to 00FFFFh 000000h to 007FFFh 0 0 0 0 1XXX 64/32 010000h to 01FFFFh 008000h to 00FFFFh 0 0 0 1 0XXX 64/32 020000h to 02FFFFh 010000h to 017FFFh 0 0 0 1 1XXX 64/32 030000h to 03FFFFh 018000h to 01FFFFh 0 0 1 0 0XXX 64/32 040000h to 04FFFFh 020000h to 027FFFh 0 0 1 0 1XXX 64/32 050000h to 05FFFFh 028000h to 02FFFFh 0 0 1 1 0XXX 64/32 060000h to 06FFFFh 030000h to 037FFFh 0 0 1 1 1XXX 64/32 070000h to 07FFFFh 038000h to 03FFFFh 0 1 0 0 0XXX 64/32 080000h to 08FFFFh 040000h to 047FFFh 0 1 0 0 1XXX 64/32 090000h to 09FFFFh 048000h to 04FFFFh 0 1 0 1 0XXX 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh 0 1 0 1 1XXX 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh 0 1 1 0 0XXX 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh 0 1 1 0 1XXX 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh 0 1 1 1 0XXX 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh 0 1 1 1 1XXX 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh 1 0 0 0 0XXX 64/32 100000h to 10FFFFh 080000h to 087FFFh 1 0 0 0 1XXX 64/32 110000h to 11FFFFh 088000h to 08FFFFh 1 0 0 1 0XXX 64/32 120000h to 12FFFFh 090000h to 097FFFh 1 0 0 1 1XXX 64/32 130000h to 13FFFFh 098000h to 09FFFFh 1 0 1 0 0XXX 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh 1 0 1 0 1XXX 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh 1 0 1 1 0XXX 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh 1 0 1 1 1XXX 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh 1 1 0 0 0XXX 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh 1 1 0 0 1XXX 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh 1 1 0 1 0XXX 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1 1 0 1 1XXX 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1 1 1 0 0XXX 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1 1 1 0 1XXX 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1 1 1 1 0XXX 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
Bank 2
Bank 1
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH)
15
MBM29DL16XTE/BE70/90
Sector Address Table (MBM29DL161BE) Bank Sector SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Address Sector Size Bank Address (Kbytes/ A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 1 1 1 1 1XXX 64/32 1 1 1 1 0XXX 64/32 1 1 1 0 1XXX 64/32 1 1 1 0 0XXX 64/32 1 1 0 1 1XXX 64/32 1 1 0 1 0XXX 64/32 1 1 0 0 1XXX 64/32 1 1 0 0 0XXX 64/32 1 0 1 1 1XXX 64/32 1 0 1 1 0XXX 64/32 1 0 1 0 1XXX 64/32 1 0 1 0 0XXX 64/32 1 0 0 1 1XXX 64/32 1 0 0 1 0XXX 64/32 1 0 0 0XXXX 64/32 1 0 0 0 0XXX 64/32 0 1 1 1 1XXX 64/32 0 1 1 1 0XXX 64/32 0 1 1 0 1XXX 64/32 0 1 1 0 0XXX 64/32 0 1 0 1 1XXX 64/32 0 1 0 1 0XXX 64/32 0 1 0 0 1XXX 64/32 0 1 0 0 0XXX 64/32 0 0 1 1 1XXX 64/32 0 0 1 1 0XXX 64/32 0 0 1 0 1XXX 64/32 0 0 1 0 0XXX 64/32 0 0 0 1 1XXX 64/32 0 0 0 1 0XXX 64/32 0 0 0 0 1XXX 64/32 0 0 0 0 0 1 1 1 8/4 0 0 0 0 0 1 1 0 8/4 0 0 0 0 0 1 0 1 8/4 0 0 0 0 0 1 0 0 8/4 0 0 0 0 0 0 1 1 8/4 0 0 0 0 0 0 1 0 8/4 0 0 0 0 0 0 0 1 8/4 0 0 0 0 0 0 0 0 8/4 (x8) Address Range 1F0000h to 1FFFFFh 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh (x16) Address Range 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh
Bank 2
Bank 1
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH).
16
MBM29DL16XTE/BE70/90
Sector Address Table (MBM29DL162TE) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address Sector Size (x8) (x16) Bank Address (Kbytes/ Address Range Address Range A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 0 0 0 0 0XXX 64/32 000000h to 00FFFFh 000000h to 007FFFh 0 0 0 0 1XXX 64/32 010000h to 01FFFFh 008000h to 00FFFFh 0 0 0 1 0XXX 64/32 020000h to 02FFFFh 010000h to 017FFFh 0 0 0 1 1XXX 64/32 030000h to 03FFFFh 018000h to 01FFFFh 0 0 1 0 0XXX 64/32 040000h to 04FFFFh 020000h to 027FFFh 0 0 1 0 1XXX 64/32 050000h to 05FFFFh 028000h to 02FFFFh 0 0 1 1 0XXX 64/32 060000h to 06FFFFh 030000h to 037FFFh 0 0 1 1 1XXX 64/32 070000h to 07FFFFh 038000h to 03FFFFh 0 1 0 0 0XXX 64/32 080000h to 08FFFFh 040000h to 047FFFh 0 1 0 0 1XXX 64/32 090000h to 09FFFFh 048000h to 04FFFFh 0 1 0 1 0XXX 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh 0 1 0 1 1XXX 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh 0 1 1 0 0XXX 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh 0 1 1 0 1XXX 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh 0 1 1 1 0XXX 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh 0 1 1 1 1XXX 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh 1 0 0 0 0XXX 64/32 100000h to 10FFFFh 080000h to 087FFFh 1 0 0 0 1XXX 64/32 110000h to 11FFFFh 088000h to 08FFFFh 1 0 0 1 0XXX 64/32 120000h to 12FFFFh 090000h to 097FFFh 1 0 0 1 1XXX 64/32 130000h to 13FFFFh 098000h to 09FFFFh 1 0 1 0 0XXX 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh 1 0 1 0 1XXX 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh 1 0 1 1 0XXX 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh 1 0 1 1 1XXX 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh 1 1 0 0 0XXX 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh 1 1 0 0 1XXX 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh 1 1 0 1 0XXX 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1 1 0 1 1XXX 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1 1 1 0 0XXX 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1 1 1 0 1XXX 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1 1 1 1 0XXX 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
Bank 2
Bank 1
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH)
17
MBM29DL16XTE/BE70/90
Sector Address Table (MBM29DL162BE) Bank Sector SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Address Sector Size Bank Address (Kbytes/ A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 1 1 1 1 1XXX 64/32 1 1 1 1 0XXX 64/32 1 1 1 0 1XXX 64/32 1 1 1 0 0XXX 64/32 1 1 0 1 1XXX 64/32 1 1 0 1 0XXX 64/32 1 1 0 0 1XXX 64/32 1 1 0 0 0XXX 64/32 1 0 1 1 1XXX 64/32 1 0 1 1 0XXX 64/32 1 0 1 0 1XXX 64/32 1 0 1 0 0XXX 64/32 1 0 0 1 1XXX 64/32 1 0 0 1 0XXX 64/32 1 0 0 0XXXX 64/32 1 0 0 0 0XXX 64/32 0 1 1 1 1XXX 64/32 0 1 1 1 0XXX 64/32 0 1 1 0 1XXX 64/32 0 1 1 0 0XXX 64/32 0 1 0 1 1XXX 64/32 0 1 0 1 0XXX 64/32 0 1 0 0 1XXX 64/32 0 1 0 0 0XXX 64/32 0 0 1 1 1XXX 64/32 0 0 1 1 0XXX 64/32 0 0 1 0 1XXX 64/32 0 0 1 0 0XXX 64/32 0 0 0 1 1XXX 64/32 0 0 0 1 0XXX 64/32 0 0 0 0 1XXX 64/32 0 0 0 0 0 1 1 1 8/4 0 0 0 0 0 1 1 0 8/4 0 0 0 0 0 1 0 1 8/4 0 0 0 0 0 1 0 0 8/4 0 0 0 0 0 0 1 1 8/4 0 0 0 0 0 0 1 0 8/4 0 0 0 0 0 0 0 1 8/4 0 0 0 0 0 0 0 0 8/4 (x8) Address Range 1F0000h to 1FFFFFh 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh (x16) Address Range 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh
Bank 2
Bank 1
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH).
18
MBM29DL16XTE/BE70/90
Sector Address Table (MBM29DL163TE) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address Sector Size (x8) (x16) Bank Address (Kbytes/ Address Range Address Range A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 0 0 0 0 0XXX 64/32 000000h to 00FFFFh 000000h to 007FFFh 0 0 0 0 1XXX 64/32 010000h to 01FFFFh 008000h to 00FFFFh 0 0 0 1 0XXX 64/32 020000h to 02FFFFh 010000h to 017FFFh 0 0 0 1 1XXX 64/32 030000h to 03FFFFh 018000h to 01FFFFh 0 0 1 0 0XXX 64/32 040000h to 04FFFFh 020000h to 027FFFh 0 0 1 0 1XXX 64/32 050000h to 05FFFFh 028000h to 02FFFFh 0 0 1 1 0XXX 64/32 060000h to 06FFFFh 030000h to 037FFFh 0 0 1 1 1XXX 64/32 070000h to 07FFFFh 038000h to 03FFFFh 0 1 0 0 0XXX 64/32 080000h to 08FFFFh 040000h to 047FFFh 0 1 0 0 1XXX 64/32 090000h to 09FFFFh 048000h to 04FFFFh 0 1 0 1 0XXX 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh 0 1 0 1 1XXX 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh 0 1 1 0 0XXX 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh 0 1 1 0 1XXX 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh 0 1 1 1 0XXX 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh 0 1 1 1 1XXX 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh 1 0 0 0 0XXX 64/32 100000h to 10FFFFh 080000h to 087FFFh 1 0 0 0 1XXX 64/32 110000h to 11FFFFh 088000h to 08FFFFh 1 0 0 1 0XXX 64/32 120000h to 12FFFFh 090000h to 097FFFh 1 0 0 1 1XXX 64/32 130000h to 13FFFFh 098000h to 09FFFFh 1 0 1 0 0XXX 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh 1 0 1 0 1XXX 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh 1 0 1 1 0XXX 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh 1 0 1 1 1XXX 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh 1 1 0 0 0XXX 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh 1 1 0 0 1XXX 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh 1 1 0 1 0XXX 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1 1 0 1 1XXX 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1 1 1 0 0XXX 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1 1 1 0 1XXX 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1 1 1 1 0XXX 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
Bank 2
Bank 1
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH)
19
MBM29DL16XTE/BE70/90
Sector Address Table (MBM29DL163BE) Bank Sector SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Address Sector Size Bank Address (Kbytes/ A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 1 1 1 1 1XXX 64/32 1 1 1 1 0XXX 64/32 1 1 1 0 1XXX 64/32 1 1 1 0 0XXX 64/32 1 1 0 1 1XXX 64/32 1 1 0 1 0XXX 64/32 1 1 0 0 1XXX 64/32 1 1 0 0 0XXX 64/32 1 0 1 1 1XXX 64/32 1 0 1 1 0XXX 64/32 1 0 1 0 1XXX 64/32 1 0 1 0 0XXX 64/32 1 0 0 1 1XXX 64/32 1 0 0 1 0XXX 64/32 1 0 0 0XXXX 64/32 1 0 0 0 0XXX 64/32 0 1 1 1 1XXX 64/32 0 1 1 1 0XXX 64/32 0 1 1 0 1XXX 64/32 0 1 1 0 0XXX 64/32 0 1 0 1 1XXX 64/32 0 1 0 1 0XXX 64/32 0 1 0 0 1XXX 64/32 0 1 0 0 0XXX 64/32 0 0 1 1 1XXX 64/32 0 0 1 1 0XXX 64/32 0 0 1 0 1XXX 64/32 0 0 1 0 0XXX 64/32 0 0 0 1 1XXX 64/32 0 0 0 1 0XXX 64/32 0 0 0 0 1XXX 64/32 0 0 0 0 0 1 1 1 8/4 0 0 0 0 0 1 1 0 8/4 0 0 0 0 0 1 0 1 8/4 0 0 0 0 0 1 0 0 8/4 0 0 0 0 0 0 1 1 8/4 0 0 0 0 0 0 1 0 8/4 0 0 0 0 0 0 0 1 8/4 0 0 0 0 0 0 0 0 8/4 (x8) Address Range 1F0000h to 1FFFFFh 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh (x16) Address Range 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh
Bank 2
Bank 1
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH).
20
MBM29DL16XTE/BE70/90
Sector Address Table (MBM29DL164TE) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Sector Address Sector Size (x8) (x16) Bank Address (Kbytes/ Address Range Address Range A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 0 0 0 0 0XXX 64/32 000000h to 00FFFFh 000000h to 007FFFh 0 0 0 0 1XXX 64/32 010000h to 01FFFFh 008000h to 00FFFFh 0 0 0 1 0XXX 64/32 020000h to 02FFFFh 010000h to 017FFFh 0 0 0 1 1XXX 64/32 030000h to 03FFFFh 018000h to 01FFFFh 0 0 1 0 0XXX 64/32 040000h to 04FFFFh 020000h to 027FFFh 0 0 1 0 1XXX 64/32 050000h to 05FFFFh 028000h to 02FFFFh 0 0 1 1 0XXX 64/32 060000h to 06FFFFh 030000h to 037FFFh 0 0 1 1 1XXX 64/32 070000h to 07FFFFh 038000h to 03FFFFh 0 1 0 0 0XXX 64/32 080000h to 08FFFFh 040000h to 047FFFh 0 1 0 0 1XXX 64/32 090000h to 09FFFFh 048000h to 04FFFFh 0 1 0 1 0XXX 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh 0 1 0 1 1XXX 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh 0 1 1 0 0XXX 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh 0 1 1 0 1XXX 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh 0 1 1 1 0XXX 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh 0 1 1 1 1XXX 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh 1 0 0 0 0XXX 64/32 100000h to 10FFFFh 080000h to 087FFFh 1 0 0 0 1XXX 64/32 110000h to 11FFFFh 088000h to 08FFFFh 1 0 0 1 0XXX 64/32 120000h to 12FFFFh 090000h to 097FFFh 1 0 0 1 1XXX 64/32 130000h to 13FFFFh 098000h to 09FFFFh 1 0 1 0 0XXX 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh 1 0 1 0 1XXX 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh 1 0 1 1 0XXX 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh 1 0 1 1 1XXX 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh 1 1 0 0 0XXX 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh 1 1 0 0 1XXX 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh 1 1 0 1 0XXX 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1 1 0 1 1XXX 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1 1 1 0 0XXX 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1 1 1 0 1XXX 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1 1 1 1 0XXX 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
Bank 2
Bank 1
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH)
21
MBM29DL16XTE/BE70/90
Sector Address Table (MBM29DL164BE) Bank Sector SA38 SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Sector Address Sector Size Bank Address (Kbytes/ A19 A18 A17 A16 A15 A14 A13 A12 Kwords) 1 1 1 1 1XXX 64/32 1 1 1 1 0XXX 64/32 1 1 1 0 1XXX 64/32 1 1 1 0 0XXX 64/32 1 1 0 1 1XXX 64/32 1 1 0 1 0XXX 64/32 1 1 0 0 1XXX 64/32 1 1 0 0 0XXX 64/32 1 0 1 1 1XXX 64/32 1 0 1 1 0XXX 64/32 1 0 1 0 1XXX 64/32 1 0 1 0 0XXX 64/32 1 0 0 1 1XXX 64/32 1 0 0 1 0XXX 64/32 1 0 0 0XXXX 64/32 1 0 0 0 0XXX 64/32 0 1 1 1 1XXX 64/32 0 1 1 1 0XXX 64/32 0 1 1 0 1XXX 64/32 0 1 1 0 0XXX 64/32 0 1 0 1 1XXX 64/32 0 1 0 1 0XXX 64/32 0 1 0 0 1XXX 64/32 0 1 0 0 0XXX 64/32 0 0 1 1 1XXX 64/32 0 0 1 1 0XXX 64/32 0 0 1 0 1XXX 64/32 0 0 1 0 0XXX 64/32 0 0 0 1 1XXX 64/32 0 0 0 1 0XXX 64/32 0 0 0 0 1XXX 64/32 0 0 0 0 0 1 1 1 8/4 0 0 0 0 0 1 1 0 8/4 0 0 0 0 0 1 0 1 8/4 0 0 0 0 0 1 0 0 8/4 0 0 0 0 0 0 1 1 8/4 0 0 0 0 0 0 1 0 8/4 0 0 0 0 0 0 0 1 8/4 0 0 0 0 0 0 0 0 8/4 (x8) Address Range 1F0000h to 1FFFFFh 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh (x16) Address Range 0F8000h to 0FFFFFh 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh
Bank 2
Bank 1
Note: The address range is A19: A-1 if in byte mode (BYTE = VIL). The address range is A19: A0 if in word mode (BYTE = VIH).
22
MBM29DL16XTE/BE70/90
Sector Group Addresses Table (MBM29DL16XTE) (Top Boot Block) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 A19 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA28 to SA30 SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA1 to SA3 Sectors SA0
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MBM29DL16XTE/BE70/90
Sector Group Addresses Table (MBM29DL16XBE) (Bottom Boot Block) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 A17 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X 0 1 0 1 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X SA38 SA35 to SA37 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA8 to SA10 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
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MBM29DL16XTE/BE70/90
Common Flash Memory Interface Code Table Description Query-unique ASCII string "QRY" Primary OEM Command Set 02h: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min (write/erase) DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VCC Max (write/erase) DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VPP Min voltage VPP Max voltage Typical timeout per single byte/word write 2N s Typical timeout for Min size buffer write 2N s Typical timeout per individual sector erase 2N ms Typical timeout for full chip erase 2N ms Max timeout for byte/word write 2N times typical Max timeout for buffer write 2N times typical Max timeout per individual sector erase 2N times typical Max timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description 02h : x8/x16 Max. number of bytes in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (zx256 bytes) A6 to A0 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h DQ15 to DQ0 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0015h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h Description Erase Block Region 2 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (zx256 bytes) Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 00h = Required Erase Suspend 02h = To Read & Write Sector Protection 00h = Not Supported X = Number of sectors in per group Sector Temporary Unprotection 01h = Supported Sector Protection Algorithm Number of Sector for Bank 2 00h = Not Supported 1Fh = MBM29DL161TE 1Ch = MBM29DL162TE 18h = MBM29DL163TE 10h = MBM29DL164TE 1Fh = MBM29DL161BE 1Ch = MBM29DL162BE 18h = MBM29DL163BE 10h = MBM29DL164BE Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported VACC (Acceleration) Supply Minimum DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV VACC (Acceleration) Supply Maximum DQ7 to DQ4: 1 V, DQ3 to DQ0: 100 mV Boot Type 02h = MBM29DL16XBE 03h = MBM29DL16XTE Program Suspend 01h = Supported A6 to A0 31h 32h 33h 34h 40h 41h 42h 43h 44h 45h 46h 47h DQ15 to DQ0 001Eh 0000h 0000h 0001h 0050h 0052h 0049h 0031h 0032h 0000h 0002h 0001h
48h 49h
0001h 0004h
4Ah
00XXh
4Bh 4Ch 4Dh
0000h 0000h 0085h
4Eh
0095h
4Fh 50h
00XXh 0001h
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MBM29DL16XTE/BE70/90
s FUNCTIONAL DESCRIPTION
* Simultaneous Operation
MBM29DL16XTE/BE have feature, which is capability of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank selection can be selected by bank address (A19 to A15) with zero latency. The MBM29DL161TE/BE have two banks which contain Bank 1 (8KB x 8 sectors) and Bank 2 (64KB x 31 sectors). The MBM29DL162TE/BE have two banks which contain Bank 1 (8KB x 8 sectors, 64KB x 3 sectors) and Bank 2 (64KB x 28 sectors). The MBM29DL163TE/BE have two banks which contain Bank 1 (8KB x 8 sectors, 64KB x 7 sectors) and Bank 2 (64KB x 24 sectors). The MBM29DL164TE/BE have two banks which contain Bank 1 (8KB x 8 sectors, 64KB x 15 sectors) and Bank 2 (64KB x 16 sectors). The simultaneous operation can not execute multi-function mode in the same bank. "Simultaneous Operation Table" shows combination to be possible for simultaneous operation. (Refer to "(8) Bank-to-bank Read/Write Timing Diagram" in sTIMING DIAGRAM.) Simultaneous Operation Table Case 1 2 3 4 5 6 7 Bank 1 Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode * Bank 2 Status Read mode Autoselect mode Program mode Erase mode * Read mode Read mode Read mode
*: By writing erase suspend command on the bank address of sector being erased, the erase operation becomes suspended so that it enables reading from or programming the remaining sectors.
* Read Mode
The MBM29DL16XTE/BE have two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time (tOE) is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from "H" to "L".
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MBM29DL16XTE/BE70/90
* Standby Mode
There are two ways to implement the standby mode on the MBM29DL16XTE/BE devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current consumed is less than 5 A max. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L"). Under this condition the current is consumed is less than 5 A max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input.
* Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29DL16XTE/BE data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To activate this mode, MBM29DL16XTE/BE automatically switch themselves to low power mode when MBM29DL16XTE/BE addresses remain stably during access fine of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 A (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and MBM29DL16XTE/BE read-out the data for changed addresses.
* Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.
* Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON'T CARES except A6, A1 A0, and (A-1). (See "MBM29DL16XTE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in sDEVICE BUS OPERATION.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29DL16XTE/BE are erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "MBM29DL16XTE/BE Command Definitions Table" in sDEVICE BUS OPERATION. (Refer to "Autoselect Command" in sCOMMAND DEFINITIONS.) Word 0 (A0 = VIL) represents the manufacturer's code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device identifier code (MBM29DL161TE = 36h and MBM29DL161BE = 39h for x8 mode; MBM29DL161TE = 2236h and MBM29DL161BE = 2239h for x16 mode), (MBM29DL162TE = 2Dh and MBM29DL162BE = 2Eh for x8 mode; MBM29DL162TE = 222Dh and MBM29DL162BE = 222Eh for x16 mode), (MBM29DL163TE = 28h and MBM29DL163BE = 2Bh for x8 mode; MBM29DL163TE = 2228h and MBM29DL163BE = 222Bh for x16 mode), 27
MBM29DL16XTE/BE70/90
(MBM29DL164TE = 33h and MBM29DL164BE = 35h for x8 mode; MBM29DL164TE = 2233h and MBM29DL164BE = 2235h for x16 mode). These two bytes/words are given in "MBM29DL16XTE/BE Sector Group Protection Verify Autoselect Codes Tables" and "Expanded Autoselect Code Tables" in sDEVICE BUS OPERATION. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See "MBM29DL16XTE/BE Sector Group Protection Verify Autoselect Codes Tables" and "Expanded Autoselect Code Tables" in sDEVICE BUS OPERATION.) In case of applying VID on A9, since both Bank 1 and Bank 2 enter Autoselect mode, the simultenous operation cannot be executed.
* Write
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to "AC Characteristics" in sELECTRICAL CHARACTERISTICS and sTIMING DIAGRAM.
* Sector Group Protection
The MBM29DL16XTE/BE feature hardware sector group protection. This feature will disable both program and erase operations in any combination of 17 sector groups of memory. (See "Sector Group Addresses Tables (MBM29DL16XTE/BE)" in sFLEXIBLE SECTOR-ERASE ARCHITECTURE). The sector group protection feature is enabled using programming equipment at the user's site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. "Sector Address Tables (MBM29DL161TE/BE, MBM29DL162TE/BE, MBM29DL163TE/BE, MBM29DL164TE/BE)" in sFLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the thirty nine (39) individual sectors, and "Sector Group Addresses Tables (MBM29DL16XTE/BE)" in sFLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector group address for each of the seventeen (17) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See "(15) AC Waveforms for Sector Group Protection" in sTIMING DIAGRAM and "(5) Sector Group Protection Algorithm" in sFLOW CHART for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the device will produce "0" for unprotected sector. In this mode, the lower order addresses, except for A6, A1, and A0 are DON'T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical "1" at DQ0 for a protected sector 28
MBM29DL16XTE/BE70/90
group. See "MBM29DL16XTE/BE Sector Group Protection Verify Autoselect Codes Tables" and "Expanded Autoselect Code Tables" in sDEVICE BUS OPERATION for Autoselect codes.
* Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the MBM29DL16XTE/BE devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to "(16) Temporary Sector Group Unprotection Timing Diagram" in sTIMING DIAGRAM and "(6) Temporary Sector Group Protection Algorithm" in sFLOW CHART.
* RESET Hardware Reset
The MBM29DL16XTE/BE devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional "tRH" before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See "(11) RESET, RY/BY Timing Diagram" in sTIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Group Unprotection for additional functionality.
* Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL16XTE/BE devices. When this pin is driven high, the devices operate in the word (16-bit) mode.The data is read and programmed at DQ15 to DQ0. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ14 to DQ8 bits are tri-stated. Refer to "(12) Timing Diagram for Word Mode Configuration", "(13) Timing Diagram for Byte Mode Configuration" and "(14) BYTE Timing Diagram for Write Operations" in sTIMING DIAGRAM.
* Boot Block Sector Protection
The Write Protect function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two "outermost" 8K byte boot sectors (MBM29DL16XTE: SA37 and SA38, MBM29DL16XBE: SA0 and SA1) independently of whether those sectors were protected or unprotected using the method described in "Sector Group Protection". The two outermost 8K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot sectors were last set to be protected or unprotected. That is, sector group protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector Group Protection".
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MBM29DL16XTE/BE70/90
* Accelerated Program Operation
MBM29DL16XTE/BE offer accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fact program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See "(18) Accelerated Program Timing Diagram" in sTIMING DIAGRAM. Erase operation at Acceleration mode is strictly prohibited.
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MBM29DL16XTE/BE70/90
s COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. Some commands are required Bank Address (BA) input. When command sequences are inputed to bank being read, the commands have priority than reading. "MBM29DL16XTE/BE Command Definitions Table" in sDEVICE BUS OPERATION defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored.
* Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to "2. AC Characteristics * Read Only Operations Characteristics" in sELECTRICAL CHARACTERISTICS and sTIMING DIAGRAM.
* Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. Following the command write, a read cycle from address (BA)00h retrieves the manufacture code of 04h. A read cycle from address (BA)01h for x16((BA)02h for x8) returns the device code (MBM29DL161TE = 36h and MBM29DL161BE = 39h for x8 mode; MBM29DL161TE = 2236h and MBM29DL161BE = 2239h for x16 mode), (MBM29DL162TE = 2Dh and MBM29DL162BE = 2Eh for x8 mode; MBM29DL162TE = 222Dh and MBM29DL162BE = 222Eh for x16 mode), (MBM29DL163TE = 28h and MBM29DL163BE = 2Bh for x8 mode; MBM29DL163TE = 2228h and MBM29DL163BE = 222Bh for x16 mode), (MBM29DL164TE = 33h and MBM29DL164BE = 35h for x8 mode; MBM29DL164TE = 2233h and MBM29DL164BE = 2235h for x16 mode). (See "MBM29DL16XTE/BE Sector Group Protection Verify Autoselect Codes Tables" and "Expanded Autoselect Code Tables" in sDEVICE BUS OPERATION.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address (BA)02h for x16 ((BA)04h for x8). Scanning the sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See "MBM29DL16XTE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in sDEVICE BUS OPERATION.)
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The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and device codes and sector group protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read. If the software (program code) for Autoselect command is stored into the Flash memory, the device and manufacture codes should be read from the other bank where is not contain the software. To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence.
* Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See "Hardware Sequence Flags Table".) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. "(1) Embedded ProgramTM Algorithm" in sFLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations.
* Program Suspend/Resume
The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address.Writing the Program Suspend command (B0h) during the Embedded Program operation immediately suspends the programming.The Program Suspend command mav also be issued during a programming operation while an erase is suspend.The bank addresses of sector being programed should be set when writing the Program Suspend command. When the Program Suspend command is written during a programming process , the device halts the program operation within 1 s and updates the status bits. After the program operation has been suspended, the system can read data from any address.The data at program-suspend address is not valid. Normal read timing and command definitions apply.
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After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses of sector being suspended should be set when writing the Program Resume command. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation.See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device in the Program Suspend mode. The device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See"Autoselect Command" for more information. The system must write the Program Resume command (address bits are "Bank Address") to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming.
* Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is "1" (See "Write Operation Status".) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) "(2) Embedded EraseTM Algorithm" in sFLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
* Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on "MBM29DL16XTE/BE Command Definitions Table" in sDEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in the sector. 33
MBM29DL16XTE/BE70/90
In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The sector erase begins after the "tTOW" time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See "Write Operation Status".) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. "(2) Embedded EraseTM Algorithm" in sFLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations.
* Erase Suspend/Resume
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being erasing or suspending should be set when writting the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin will be at High-Z and the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See "DQ2".) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. 34
MBM29DL16XTE/BE70/90
To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
* Extended Command
(1) Fast Mode MBM29DL16XTE/BE have Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to "(7) Embedded ProgramTM Algorithm for Fast Mode" in sFLOW CHART.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to "(7) Embedded ProgramTM Algorithm for Fast Mode" in sFLOW CHART.) (3) Extended Sector Group Protection In addition to normal sector group protection, the MBM29DL16XTE/BE have Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The extended sector group protection requires VID on RESET pin only. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60h). A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logical "0", please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to "(17) Extended Sector Group Protection Timing Diagram" in sTIMING DIAGRAM and "(8) Extended Sector Group Protection Algorithm" in sFLOW CHART.) (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ15 to DQ8) is "0" in word mode (16 bit) read. Refer to "Common Flash Memory Interface Code Table" in sFLEXBLE SECTORERASE ARCHITECTURE. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See "Common Flash Memory Interface Code Table" in sFLEXIBLE SECTOR-ERASE ARCHITECTURE.)
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* HiddenROM Region
The HiddenROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 64 Kbytes in length and is stored at the same address of the 8 KB x8 sectors. The MBM29DL16XTE occupies the address of the byte mode 1F0000h to 1FFFFFh (word mode 0F8000h to 0FFFFFh) and the MBM29DL16XBE type occupies the address of the byte mode 000000h to 00FFFFh (word mode 000000h to 007FFFh). After the system has written the Enter HiddenROM command sequence, the system may read the HiddenROM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.
* HiddenROM Entry Command
MBM29DL16XTE/BE have a HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However, once it is protected, it is impossible to unprotect, so please use this with caution. HiddenROM area is 64 Kbyte and in the same address area of 8 KB sectors. The address of top boot is 1F0000h to 1FFFFFh at byte mode (0F8000h to 0FFFFFh at word mode) and the bottom boot is 000000h to 00FFFFh at byte mode (000000h to 007FFFh at word mode). These areas are normally the boot block area (8 KB x 8 sectors). Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called as HiddenROM mode when the HiddenROM area appears. Sector other than the boot block area could be read during HiddenROM mode. Read/program/earse of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset command sequence. In case of MBM29DL161TE/BE, whose Bank 1 size is 0.5 Mbit, the simultaneous operation cannot execute multi-function mode between the HiddenROM area and Bank 2 Region.
* HiddenROM Program Command
To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in the past except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address other than the HiddenROM area is selected to program, the data of the address will be changed.
* HiddenROM Erase Command
To erase the HiddenROM area, write the HiddenROM erase command sequence during HiddenROM mode. This command is the same as the sector erase command in the past except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address other than the HiddenROM area is selected, the data of the sector will be changed.
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MBM29DL16XTE/BE70/90
* HiddenROM Protect Command
There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command (60h), set the sector address in the HiddenROM area and (A6, A1, A0) = (0,1,0), and write the sector group protect command (60h) during the HiddenROM mode. The same command sequence could be used because except that it is in the HiddenROM mode and that it does not apply high voltage to RESET pin, it is the same as the extension sector group protect in the past. Please refer to "Extended Command (3) Extended Sector Group Protection" for details of extention sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A1, A0) = (0,1,0), and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the HiddenROM area, and read. When "1" appears to DQ0, the protect setting is completed. "0" will appear to DQ0 if it is not protected. Please apply write pulse agian. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same as the sector group protect in the past. Please refer to "Sector Group Protection" in sFUNCTIONAL DESCRIPTION for details of sector group protect setting Other sector group will be effected if the address other than the HiddenROM area is selected for the sector group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay closest attention.
* Write Operation Status
Detailed in "Hardware Sequence Flags Table" are all the status flags that can determine the status of the bank for the current mode operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. Information on DQ2 is address sensitive. This means that if an address from an erasing sector is consectively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a nonerasing sector is consectively read. This allows the user to determine which sectors are erasing and which are not. The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] , [2] , [3] , the DQ6 is toggling in the case of [1] and [3]. In case of [2], the data of memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in the [1] and [3]. In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is outputted.
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MBM29DL16XTE/BE70/90
Hardware Sequence Flags Table Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) In Progress Mode Erase Suspend Program (Non-Erase Suspended Sector) Program Suspend Read Program (Program Suspended Sector) Suspended Program Suspend Read Mode (Non-Program Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode DQ7 DQ7 0 1 Data DQ7 Data Data DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle Data Data Toggle Toggle Toggle DQ5 0 0 0 DQ3 0 1 0 DQ2 1 Toggle*1 Toggle Data 1 *2 Data Data 1 N/A N/A
Data Data 0 0
Data Data Data Data 1 1 1 0 1 0
*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address indicates logic "1" at the DQ2 bit.
* DQ7 Data Polling
The MBM29DL16XTE/BE devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in "(3) Data Polling Algorithm" in sFLOW CHART. For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 s, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the MBM29DL16XTE/BE data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are 38
MBM29DL16XTE/BE70/90
driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See "Hardware Sequence Flags Table".) See "(6) AC Waveforms for Data Polling during Embedded Algorithm Operations" in sTIMING DIAGRAM for the Data Polling timing specifications and diagrams.
* DQ6 Toggle Bit I
The MBM29DL16XTE/BE also feature the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data from the devices will result in DQ6 toggling between "1" and "0". Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 s and then stop toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erasing or is erase-suspended. When a bank is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause DQ6 to toggle. To operate toggle bit function properly, CE or OE must be high when bank address is changed. See "(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations" in sTIMING DIAGRAM for the Toggle Bit I timing specifications and diagrams.
* DQ5 Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in "MBM29DL16XTE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in sDEVICE BUS OPERATION. The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the 39
MBM29DL16XTE/BE70/90
DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence.
* DQ3 Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags Table".
* DQ2 Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Toggle Bit Status Table" and "(9) DQ2 vs. DQ6" in sTIMING DIAGRAM. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed.
* Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on "DQ5"). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase 40
MBM29DL16XTE/BE70/90
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the begining of the algorithm when it returns to determine the status of the operation. (Refer to "(4) Toggle Bit Algorithm" in sFLOW CHART.) Toggle Bit Status Table Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle*1 Toggle 1*2
*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle. *2 : Reading from the non-erase suspend sector address indicates logic "1" at the DQ2 bit.
* RY/BY Ready/Busy
The MBM29DL16XTE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/ write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands. If the MBM29DL16XTE/BE are placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to "(10) RY/BY Timing Diagram during Program/Erase Operations" and "(11) RESET, RY/BY Timing Diagram" in sTIMING DIAGRAM for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, the pull-up resistor needs to be connected to VCC ; multiples of devices may be connected to the host system via more than one RY/BY pin in parallel.
* Data Protection
The MBM29DL16XTE/BE are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise.
41
MBM29DL16XTE/BE70/90
* Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (Min). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min). If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
* Write Pulse "Glitch" Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
* Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logic "0" while OE is a logic "1".
* Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up.
* Sector Group Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids both program and erase commands that are addressed to protected sectors. Any command to program or erase addressed to protected sector are ignored (see "Sector Group Protection" in s FUNCTIONAL DESCRIPTION).
42
MBM29DL16XTE/BE70/90
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All Pins except A9, OE, RESET *1, *2 Power Supply Voltage *1 A9, OE, and RESET *1, *3 WP/ACC * *
1, 4
Symbol Tstg TA VIN, VOUT VCC VIN VACC
Rating Min -55 -40 -0.5 -0.5 -0.5 -0.5 Max +125 +85 VCC+0.5 +4.0 +13.0 +10.5
Unit C C V V V V
*1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCC) does not exceed 9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *4 : Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature Power Supply Voltage* Symbol TA VCC Conditions
MBM29DL16XTE/BE70/90 MBM29DL16XTE/BE70/90
Value Min -40 +2.7 Max +85 +3.6
Unit C V
* : Voltage is defined on the basis of VSS = GND = 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
43
MBM29DL16XTE/BE70/90
s MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
+0.6 V -0.5 V -2.0 V
20 ns
20 ns
20 ns
Maximum Undershoot Waveform
20 ns
V CC +2.0 V V CC +0.5 V +2.0 V
20 ns 20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V +13.0 V V CC +0.5 V
20 ns 20 ns
Note: This waveform is applied for A9, OE, and RESET.
Maximum Overshoot Waveform 2
44
MBM29DL16XTE/BE70/90
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current WP/ACC Accelerated Program Current Symbol ILI ILO ILIT ILIA Conditions VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE, RESET = 12.5 V VCC = VCC Max, WP/ACC = VACC Max CE = VIL, OE = VIH, f = 5 MHz VCC Active Current *1 ICC1 CE = VIL, OE = VIH, f = 1 MHz VCC Active Current *2 VCC Current (Standby) VCC Current (Standby, Reset) VCC Current (Automatic Sleep Mode) *5 VCC Active Current *6 (Read-While-Program) VCC Active Current *6 (Read-While-Erase) VCC Active Current (Erase-Suspend-Program) Input Low Voltage Input High Voltage Voltage for Autoselect and Sector Group Protection (A9, OE, RESET) *3, *4 Voltage for WP/ACC Sector Group Protection/Unprotection and Program Acceleration *4 Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage ICC2 ICC3 ICC4 ICC5 CE = VIL, OE = VIH VCC = VCC Max, CE = VCC 0.3 V, RESET = VCC 0.3 V, WP/ACC = VCC 0.3 V VCC = VCC Max, RESET = VSS 0.3 V VCC = VCC Max, CE = VSS 0.3 V, RESET = VCC 0.3 V, VIN = VCC 0.3 V or VSS 0.3 V CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH -- -- -- Byte Word Byte Word Byte Word Byte Word Value Min -1.0 -1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -0.5 2.0 11.5 Typ -- -- -- -- -- -- -- -- -- 1 1 1 -- -- -- -- -- -- -- 12 Max +1.0 +1.0 +35 20 13 15 7 7 35 5 5 5 48 50 48 50 35 +0.6 VCC+0.3 12.5 Unit A A A mA mA mA mA A A A
ICC6 ICC7 ICC8 VIL VIH VID
mA mA mA V V V
VACC VOL VOH1 VOH2 VLKO
-- IOL = 4.0 mA, VCC = VCC Min IOH = -2.0 mA, VCC = VCC Min IOH = -100 A --
8.5 -- 2.4 VCC - 0.4 2.3
9.0 -- -- -- 2.4
9.5 0.45 -- -- 2.5
V V V V V
(Continued)
45
MBM29DL16XTE/BE70/90
(Continued)
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : This timing is only for Sector Group Protection operation and Autoselect mode. *4 : Applicable for only VCC. *5 : Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *6 : Embedded Algorithm (program or erase) is in progress. (@5 MHz)
46
MBM29DL16XTE/BE70/90
2. AC Characteristics
* Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE to BYTE Switching Low or High Symbol JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- -- Standard tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH Conditions -- CE = VIL OE = VIL OE = VIL -- -- -- -- -- -- 70 Min 70 0 Max 70 70 30 25 25 20 5 Min 90 0 90 Max 90 90 35 30 30 20 5 Unit ns ns ns ns ns ns ns s ns
Note: Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29DL16XTE/BE70) 1 TTL gate and 100 pF (MBM29DL16XTE/BE90) Input rise and fall times: 5 ns Input pulse levels: 0.0 V or 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V
3.3 V Diode = 1N3064 or Equivalent
2.7 k
Device Under Test
6.2 k CL Diode = 1N3064 or Equivalent
Note : CL = 30 pF including jig capacitance (MBM29DL16XTE/BE70) CL = 100 pF including jig capacitance (MBM29DL16XTE/BE90) Test Conditions
47
MBM29DL16XTE/BE70/90
* Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling Symbol
JEDEC
Standard
70 Min 70 0 12 45 0 30 0 0 10 20 20 0 0 0 0 0 0 35 35 25 25 50 500 500 4 100 4 4 0 Typ Max 8 16 1 Min 90 0 15 45 0 35 0 0 10 20 20 0 0 0 0 0 0 35 35 30 30 50 500 500 4 100 4 4 0
90 Typ Max 8 16 1
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s ns ns s s s s ns
tAVAV tAVWL -- tWLAX -- tDVWH tWHDX -- -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL Byte Word
1
tWC tAS tASO tAH tAHT tDS tDH tOEH tCEPH tOEPH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP tCSP tRB
CE High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Programming Operation Sector Erase Operation* VCC Setup Time Rise Time to VID *2 Rise Time to VACC*
3 2
tWHWH1 tWHWH2 -- -- -- -- -- -- -- --
Voltage Transition Time* Write Pulse Width*2
OE Setup Time to WE Active*2 CE Setup Time to WE Active * Recover Time From RY/BY
2
(Continued)
48
MBM29DL16XTE/BE70/90
(Continued)
Parameter RESET Pulse Width RESET High Level Period Before Read BYTE Switching Low to Output High-Z BYTE Switching High to Output Active Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time *1 : This does not include preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is limited for Accelerated Protection operation. Symbol
JEDEC
Standard
70 Min 500 200 Typ Max 25 70 90 70 50 20 Min 500 200
90 Typ Max 30 90 90 90 50 20
Unit ns ns ns ns ns ns s s
-- -- -- -- -- -- -- --
tRP tRH tFLQZ tFHQV tBUSY tEOE tTOW tSPD
s ERASE AND PROGRAMMING PERFORMANCE
Value Parameter Min Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle -- -- -- -- 100,000 Typ 1 16 8 -- -- Max 10 360 300 50 -- s s s s cycle Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Unit Comments
49
MBM29DL16XTE/BE70/90
s PIN CAPACITANCE
1. TSOP(1) pin capacitance
Value Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Condition Min VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ 6.0 8.5 8.0 17.0 Max 7.5 12.0 10.0 18.0 pF pF pF pF Unit
Notes : * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance.
2. FBGA pin capacitance
Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Condition VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Value Min Typ 7.0 9.5 9.0 17.0 Max 9.0 13.0 11.0 18.0 Unit pF pF pF pF
Notes : * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance.
50
MBM29DL16XTE/BE70/90
s TIMING DIAGRAM
* Key to Switching Waveforms
WAVEFORM
INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L" Any Change Permitted Does Not Apply
OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is HighImpedance "Off" State
(1) AC Waveforms for Read Operations
tRC
Address
Address Stable
tACC
CE
tOE tDF
OE
tOEH
WE
tCE tOH
Outputs
High-Z
Output Valid
High-Z
51
MBM29DL16XTE/BE70/90
(2) AC Waveforms for Hardware Reset/Read Operations
tRC
Address
tACC tRH
Address Stable
CE
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Output Valid
(3) AC Waveforms for Alternate WE Controlled Program Operations
3rd Bus Cycle Address
555h tWC tAS PA tAH
Data Polling
PA tRC
CE
tCS tCH tCE
OE
tGHWL tWP tWPH tWHWH1 tOE
WE
tDS tDH tDF tOH
Data
A0h
PD
DQ7
DOUT
DOUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. * These waveforms are for the x 16 mode. These address differ from x 8 mode. 52
MBM29DL16XTE/BE70/90
(4) AC Waveforms for Alternate CE Controlled Program Operations
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CE
tDS tDH
Data
A0h
PD
DQ7
DOUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. * These waveforms are for the x 16 mode. These address differ from x 8 mode.
53
MBM29DL16XTE/BE70/90
(5) AC Waveforms for Chip/Sector Erase Operations
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
CE
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS AAh
tDH 55h 80h AAh 55h
10h for Chip Erase 10h/ 30h
Data
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase. Note : These waveforms are for the x16 mode. The addresses differ from x8 mode.
54
MBM29DL16XTE/BE70/90
(6) AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
DQ7
Data DQ7 DQ7 = Valid Data
High-Z
tWHWH1 or tWHWH2
DQ6 to DQ0
Data tBUSY
DQ6 to DQ0 = Output Flag tEOE
DQ6 to DQ0 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation).
55
MBM29DL16XTE/BE70/90
(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
Address
tAHT tASO tAHT tAS
CE
tCEPH
WE
tOEH
tOEPH tOEH
OE
tDH tOE tCE
DQ6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
*
Stop
Toggling
Output Valid
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
56
MBM29DL16XTE/BE70/90
(8) Bank-to-bank Read/Write Timing Diagram
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
Address
BA1
tAS
BA2 (555h)
tAH
BA1
tACC tCE
BA2 (PA)
BA1
tAS tAHT
BA2 (PA)
CE
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF
DQ
Valid Output
Valid Intput (A0h)
Valid Output
Valid Intput (PD)
Valid Output
Status
Note: This is the example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address corresponding to Bank 1. BA2: Address corresponding to Bank 2. (9) DQ2 vs. DQ6
Enter Embedded Erasing WE
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2* Toggle DQ2 and DQ6 with OE or CE
* : DQ2 is read from the erase-suspended sector.
57
MBM29DL16XTE/BE70/90
(10) RY/BY Timing Diagram during Program/Erase Operations
CE
Rising edge of the last write pulse
WE
Entire programming or erase operations
RY/BY
tBUSY
(11) RESET, RY/BY Timing Diagram
WE
RESET
tRP tRB
RY/BY
tREADY
(12) Timing Diagram for Word Mode Configuration
CE
tCE
BYTE
DQ14 to DQ0
tELFH
Data Output (DQ7 to DQ0) tFHQV
Data Output (DQ14 to DQ0)
DQ15/A-1
A-1
DQ15
58
MBM29DL16XTE/BE70/90
(13) Timing Diagram for Byte Mode Configuration
CE
BYTE
tELFL
DQ14 to DQ0
Data Output (DQ14 to DQ0) tACC
Data Output (DQ7 to DQ0)
DQ15/A-1
DQ15 tFLQZ
A-1
(14) BYTE Timing Diagram for Write Operations
Falling edge of the last write signal
CE or WE
BYTE
tAS
Input Valid
tAH
59
MBM29DL16XTE/BE70/90
(15) AC Waveforms for Sector Group Protection
A19, A18, A17 A16, A15, A14 A13, A12 A6, A0
SPAX
SPAY
A1 VID VIH A9
tVLHT
VID VIH OE
tVLHT tOESP tWPP tVLHT tVLHT
WE
tCSP
CE
Data
tVCS tOE
01h
VCC
SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected Note: A-1 is VIL on byte mode.
60
MBM29DL16XTE/BE70/90
(16) Temporary Sector Group Unprotection Timing Diagram
VCC
tVCS
tVIDR tVLHT
VID VIH RESET
CE
WE
tVLHT Program or Erase Command Sequence tVLHT
RY/BY
Unprotection period
61
MBM29DL16XTE/BE70/90
(17) Extended Sector Group Protection Timing Diagram
VCC VID RESET
tVCS
tVLHT tVIDR tWC tWC
Address
SPAX
SPAX
SPAY
A6, A0
A1
CE
OE
tWP
TIME-OUT
WE
Data
60h
60h
40h
tOE
01h
60h
SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min) Note : A-1 is VIL on byte mode.
62
MBM29DL16XTE/BE70/90
(18) Accelerated Program Timing Diagram
VCC
tVCS
tVACCR tVLHT
VACC VIH WP/ACC
CE
WE
tVLHT Program Command Sequence tVLHT
RY/BY
Acceleration period
63
MBM29DL16XTE/BE70/90
s FLOW CHART
(1) Embedded ProgramTM Algorithm EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See below)
Data Polling Embedded Program Algorithm in program
No
Verify Data ? Yes
Increment Address
No
Last Address ? Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Notes : * The sequence is applied for x 16 mode. * The addresses differ from x 8 mode.
64
MBM29DL16XTE/BE70/90
(2) Embedded EraseTM Algorithm EMBEDDED ALGORITHMS
Start
Write Erase Command Sequence (See below)
Data Polling Embedded Program Algorithm in program
No
Data = FFh ?
Yes
Erasure Completed Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh
Chip Erase Command Sequence (Address/Command): 555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address/30h
Sector Address/30h
Additional sector erase commands are optional.
Sector Address/30h
Notes : * The sequence is applied for x 16 mode. * The addresses differ from x 8 mode.
65
MBM29DL16XTE/BE70/90
(3) Data Polling Algorithm
Start
Read Byte (DQ7 to DQ0) Addr. = VA
DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA
Yes
VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation. = Any of the sector addresses within the sector not being protected during chip erase operation.
DQ7 = Data? * No Fail
Yes
Pass
* : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
66
MBM29DL16XTE/BE70/90
(4) Toggle Bit Algorithm
Start
Read DQ7 to DQ0 Addr. = VA Read DQ7 to DQ0 Addr. = VA
*1
VA = Bank address being executed Embedded Algorithm.
*1
DQ6 = Toggle ? Yes No DQ 5 = 1? Yes Read DQ7 to DQ0 Addr. = VA
No
*1, *2
Read DQ7 to DQ0 *1, *2 Addr. = VA
DQ6 = Toggle ? Yes Program/Erase Operation Not Complete. Write Reset Command
No
Program/Erase Operation Complete
*1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changing to "1".
67
MBM29DL16XTE/BE70/90
(5) Sector Group Protection Algorithm
Start
Setup Sector Group Addr. (A19, A18, A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID, CE = VIL, RESET = VIH A6 = A0 = VIL, A1 = VIH Activate WE Pulse
Increment PLSCNT
Time out 100 s
WE = V IH, CE = OE = V IL (A 9 should remain V ID)
Read from Sector Group (Addr. = SPA, A1 = VIH, A6 = V0 = VIL) * No No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command Data = 01h? Yes Yes Protect Another Sector Group ? No Remove VID from A9 Write Reset Command
Device Failed
Sector Group Protection Completed
* : A-1 is V IL on byte mode.
68
MBM29DL16XTE/BE70/90
(6) Temporary Sector Group Unprotection Algorithm
Start
RESET = VID *1
Perform Erase or Program Operations
RESET = VIH
Temporary Sector Group Unprotection Completed*2
*1 : All protected sector groups are unprotected. *2 : All previously protected sector groups are protected once again.
69
MBM29DL16XTE/BE70/90
(7) Extended Sector Group Protection Algorithm
Start
RESET = VID
Wait to 4 s
Device is Operating in Temporary Sector Group Unprotection Mode
No
Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h
PLSCNT = 1
To Sector Group Protection Write 60h to Sector Address (A6 = A0 = VIL, A1 = VIH) Time out 250 s Setup Next Sector Group Address
Increment PLSCNT
To Verify Sector Group Protection Write 40h to Sector Address (A6 = A0 = VIL, A1 = VIH) Read from Sector Group Address (Addr. = SPA, A6 = A0 = VIL, A1 = VIH) No No PLSCNT = 25? Yes Data = 01h? Yes Protection Other Sector Group? No Device Failed Remove VID from RESET Write Reset Command Yes
Remove VID from RESET Write Reset Command
Sector Group Protection Completed
70
MBM29DL16XTE/BE70/90
(8) Embedded ProgramTM Algorithm for Fast Mode FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
Set Fast Mode
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling
Verify Data ? Yes Increment Address No Last Address ? Yes Programming Completed
No
In Fast Program
(BA)XXXh/90h Reset Fast Mode XXXh/F0h
Notes: * The sequence is applied for x 16 mode. * The addresses differ from x 8 mode.
71
MBM29DL16XTE/BE70/90
s ORDERING INFORMATION
Part No. MBM29DL161TE-70TN MBM29DL161TE-90TN MBM29DL162TE-70TN MBM29DL162TE-90TN MBM29DL163TE-70TN MBM29DL163TE-90TN MBM29DL164TE-70TN MBM29DL164TE-90TN MBM29DL161TE-70TR MBM29DL161TE-90TR MBM29DL162TE-70TR MBM29DL162TE-90TR MBM29DL163TE-70TR MBM29DL163TE-90TR MBM29DL164TE-70TR MBM29DL164TE-90TR MBM29DL161TE-70PBT MBM29DL161TE-90PBT MBM29DL162TE-70PBT MBM29DL162TE-90PBT MBM29DL163TE-70PBT MBM29DL163TE-90PBT MBM29DL164TE-70PBT MBM29DL164TE-90PBT MBM29DL161BE-70TN MBM29DL161BE-90TN MBM29DL162BE-70TN MBM29DL162BE-90TN MBM29DL163BE-70TN MBM29DL163BE-90TN MBM29DL164BE-70TN MBM29DL164BE-90TN MBM29DL161BE-70TR MBM29DL161BE-90TR MBM29DL162BE-70TR MBM29DL162BE-90TR MBM29DL163BE-70TR MBM29DL163BE-90TR MBM29DL164BE-70TR MBM29DL164BE-90TR MBM29DL161BE-70PBT MBM29DL161BE-90PBT MBM29DL162BE-70PBT MBM29DL162BE-90PBT MBM29DL163BE-70PBT MBM29DL163BE-90PBT MBM29DL164BE-70PBT MBM29DL164BE-90PBT 72 Package Access Tome 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 Remarks
48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend
48-pin plastic TSOP (1) (FPT-48P-M20) Reverse Bend
Top Sector
48-pin plastic FBGA (BGA-48P-M11)
48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend
48-pin plastic TSOP (1) (FPT-48P-M20) Reverse Bend
Bottom Sector
48-pin plastic FBGA (BGA-48P-M11)
MBM29DL16XTE/BE70/90
MBM29DL16X
T
E
70
TN
PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout TR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PBT = 48-Pin Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION
BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector
DEVICE NUMBER/DESCRIPTION MBM29DL16X 16 Mega-bit (2 M x 8-Bit or 1 M x 16-Bit) CMOS Flash Memory 3.0 V-only Read, Program, and Erase
73
MBM29DL16XTE/BE70/90
s PACKAGE DIMENSIONS
48-pin plastic TSOP(1) (FPT-48P-M19)
Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
48
LEAD No.
1
INDEX
Details of "A" part
0.25(.010)
0~8
0.600.15 (.024.006)
24
25
20.000.20 (.787.008)
* 12.000.20
(.472.008) 1.10 -0.05
+0.10 +.004
* 18.400.20
(.724.008)
.043 -.002 (Mounting height)
0.50(.020)
"A"
0.10(.004)
0.17 -0.08 .007 -.003
C
+0.03 +.001
0.100.05 (.004.002) (Stand off height) 0.220.05 (.009.002) 0.10(.004)
M
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches). Note : The values in parentheses are reference values. Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
48
48-pin plastic TSOP(1) (FPT-48P-M20)
LEAD No.
1
INDEX
Details of "A" part 0.600.15 (.024.006)
0~8 0.25(.010)
24
25
0.17 -0.08
+0.03 +.001
0.10(.004)
.007 -.003 0.50(.020)
0.220.05 (.009.002)
0.10(.004)
M
0.100.05 (.004.002) (Stand off height)
"A"
1.10 -0.05
+0.10 +.004
* 18.400.20
(.724.008) 20.000.20 (.787.008)
.043 -.002 (Mounting height)
* 12.000.20(.472.008)
C
2003 FUJITSU LIMITED F48030S-c-6-7
Dimensions in mm (inches). Note : The values in parentheses are reference values.
(Continued)
74
MBM29DL16XTE/BE70/90
(Continued)
48-pin plastic FBGA (BGA-48P-M11)
8.000.20(.315.008) 1.05 -0.10 .041 -.004 (Mounting height) 0.380.10(.015.004) (Stand off)
+0.15 +.006
(5.60(.220)) 0.80(.031)TYP
6 5 INDEX 6.000.20 (.236.008) 4 (4.00(.157)) 3 2 1
H C0.25(.010)
G
F
E
D
C
B
A
M
48-o0.450.10 (48-o.018.004)
o0.08(.003)
0.10(.004)
C
2001 FUJITSU LIMITED B48011S-c-5-3
Dimensions in mm (inches). Note : The values in parentheses are reference values.
75
MBM29DL16XTE/BE70/90
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0311 (c) FUJITSU LIMITED Printed in Japan

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